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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21378-2E
ASSP
Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler
MB15E07SR
DESCRIPTION
The Fujitsu MB15E07SR is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler. The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation. The supply voltage range is between 2.7 V and 5.0 V. A refined charge pump supplies well-balanced output currents of 1.0 mA and 4.0 mA. The charge pump current is selectable by serial data. The phase noise of MB15E07SR was drastically improved comparing wuth the former single PLL, MB15E07SL. The data format of serial data and the pin assignments except for P R and OSCout pins are same as the former , one, so it is easy to replace the former one. MB15E07SR is ideally suited for the base station of GSM (Global System for Mobile Communications) and PCS.
FEATURES
* * * * High frequency operation: 2.5 GHz Max Low power supply voltage: VCC = 2.7 V to 5.0 V Ultra Low power supply current:ICC = 8.0 mA Typ (VCC = Vp = 3.75 V, Ta = +25C, in locking state) Direct power saving function:Power supply current in power saving mode Typ 0.1 A (VCC = Vp = 3.75 V, Ta = +25C) * Dual modulus prescaler: 32/33 or 64/65 (Continued)
PACKAGES
16-pin plastic TSSOP 16-pad plastic BCC
(LCC-16P-M06) (FPT-16P-M07)
MB15E07SR
(Continued) * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Software selectable charge pump current * On-chip phase control for phase comparator * Built-in digital locking detector circuit to detect PLL locking and unlocking * Operating temperature: Ta = -40 C to +85 C
PIN ASSIGNMENTS
16-pin TSSOP
OSCIN N.C. VP VCC DO GND Xfin fin 1 2 3 4 5 6 7 8
Top view
16-pad BCC
N.C. N.C. LD/fout N.C. PS LE Data Clock N.C. VP VCC DO GND Xfin 1 2 16 15 14 13 3 Top view 12 4 11 5 10 6 7 8 9 N.C. LD/fout N.C. PS LE Data
16 15 14 13 12 11 10 9
OSCIN N.C.
fin Clock
(FPT-16P-M07)
(LCC-16P-M06)
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MB15E07SR
PIN DESCRIPTIONS
Pin no. TSSOP 1 2 3 4 5 6 7 8 9 10 11 BCC 16 1 2 3 4 5 6 7 8 9 10 Pin name OSCIN N.C. VP VCC DO GND Xfin fin Clock Data LE I/O I - - - O - I I I I I Descriptions Programmable reference divider input. Connection to a TCXO. No connection. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. Ground. Prescaler complementary input, which should be grounded via a capacitor. Prescaler input. Connection to an external VCO should be done via AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H"; Normal mode PS = "L"; Power saving mode No connection. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = "H"; outputs fout (fr/fp monitoring output) LDS = "L"; outputs LD ("H" at locking, "L" at unlocking.) No connection. No connection.
12 13 14 15 16
11 12 13 14 15
PS N.C. LD/fout N.C. N.C.
I - O - -
3
MB15E07SR
BLOCK DIAGRAM
1 OSCIN(16)
fr
Reference oscillator circuit
Binary 14-bit reference couter 14-bit latch
SW
FC
LDS CS
4-bit latch
Phase comparator
12 PS(11)
Intermittent mode control (power save)
C N T
Lock detector 19-bit shift register
11 LE (10)
1-bit control latch
LD/fr/fp selector
14 LD/fout (13)
7-bit latch
11-bit latch
Charge pump
3 (2) VP 5 (4) DO
Data
10 (9)
Binary 7-bit swallow counter
Binary 11-bit programmable counter
fp
Clock 9 (8)
Xfin 7 (6) 8 fin (7)
Prescaler 32/33 64/65
SW
6 GND (5) 4 VCC (3)
O : TSSOP ( ) : BCC
4
MB15E07SR
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO VO Tstg Condition - - - Except Do Do - Rating Min -0.5 VCC -0.5 GND GND -55 Max 5.5 6.0 VCC + 0.5 VCC VP +125 Unit V V V V V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min 2.7 VCC GND -40 Typ 3.75 - - - Max 5.0 5.5 VCC +85 Unit V V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15E07SR
ELECTRICAL CHARACTERISTICS
(VCC = 2.7 V to 5.0 V, Ta = -40C to +85C) Parameter Power supply current*1 Power saving current Operating frequency fin OSCIN fin*3 OSCIN* "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level output voltage "L" level output voltage "H" level output voltage "L" level output voltage High impedance cutoff current "H" level output current "L" level output current "H" level output current Do "L" level output current IDOL
3
Symbol ICC*1 IPS fIN OSCIN Pfin VOSC VIH VIL IIH*4 IIL* IIL*
4
Condition fIN = 2500 MHz, VCC = VP = 3.75 V PS = "L" 50 system - 100 MHz to 300 MHz 300 MHz to 2500 MHz - - - - - - - VCC = VP = 3.75 V, IOH = -1 mA VCC = VP = 3.75 V, IOL = 1 mA VCC = VP = 3.75 V, IDOH = -0.5 mA VCC = VP = 3.75 V, IDOL = 0.5 mA VCC = VP = 3.75 V, VOFF = 0.5 V to VP - 0.5 V - - VCC = 3.75 V, VP = 3.75 V, VDO = VP/2 Ta = +25C CS bit = "1" CS bit = "0" CS bit = "1" CS bit = "0"
Value Min - - 100 3 -6 -15 0.5 VCC x 0.7 - -1.0 -1.0 0 -100 VCC - 0.4 - VP - 0.4 - - - 1.0 - - - - - - - Typ 8.0 0.1* - - - - - - - - - - - - - - - - - - -4.0 -1.0 4.0 1.0 5 10 3
2
Max - 20 2500 40 +2 +2 VCC - VCC x 0.3 +1.0 +1.0 +100 0 - 0.4 - 0.4 2.5 -1.0 - - - - - - - -
Unit mA A MHz MHz dBm dBm Vp-p V A A V V nA mA
Input sensitivity
Data, Clock, LE, PS Data, Clock, LE, PS OSCIN LD/fout Do Do LD/fout
IIH
4
VOH VOL VDOH VDOL IOFF IOH IOL IDOH*4
mA
IDOL/IDOH IDOMT*5 VDO = VP/2 Charge pump current rate vs VDO vs Ta IDOVD*6 0.5 V VDO VP - 0.7 V IDOTA*7 - 40C Ta +85C
% % %
*1: Conditions; fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25C, in locking state. *2: VCC = VP = 3.75 V, fosc = 13 MHz, Vosc = 1.2 VPP , Ta = +25C, in power saving mode *3: AC coupling. 1000 pF capacitor is connected under the condition of minimum operating frequency. *4: The symbol "-" (minus) means direction of current flow. *5: VCC = VP = 3.0 V, Ta = +25C (||I3| - |I4||) / [(|I3| + |I4|) /2] x 100(%) (Continued)
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MB15E07SR
(Continued) *6: VCC = VP = 3.0 V, Ta = +25C [(||I2| - |I1||) /2] / [(|I1| + |I2|) /2] x 100(%) (Applied to each IDOL, IDOH) *7: VCC = VP = 3.0 V, VDO = VP/2 (||IDO(+85C)| - |IDO(-40C)|| /2) / (|IDO(+85C)| + |IDO(-40C)| /2) x 100(%) (Applied to each IDOL, IDOH)
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 Vp/2 Vp - 0.7 V Vp
Charge Pump Output Voltage (V)
7
MB15E07SR
FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) M : Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control bit (CNT) H L (1) Shift Register Configuration Programmable Reference Counter LSB Data Flow 1 C N T 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5 7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 R 12 14 R 13 15 R 14 16 17 18 19 MSB Destination of serial data For the programmable reference divider For the programmable divider
SW
FC LDS CS
CNT R1 to R14 SW FC LDS CS
: Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (32/33 or 64/65) : Phase control bit for the phase comparator : LD/fOUT signal select bit : Charge pump current select bit
[Table 1] [Table 2] [Table 5] [Table 8] [Table 7] [Table 6]
Note: Start data input with MSB first.
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MB15E07SR
Programmable Counter LSB 1 C N T 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7 MSB Data Flow 9 N 1 10 N 2 11 N 3 12 N 4 13 N 5 14 N 6 15 N 7 16 N 8 17 N 9 18 N 10 19 N 11
CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Data input with MSB first.
[Table 1] [Table 3] [Table 4]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R14 0 0 1 R13 0 0 1 R12 0 0 1 R11 0 0 1 R10 0 0 1 R9 0 0 1 R8 0 0 1 R7 0 0 1 R6 0 0 1 R5 0 0 1 R4 0 0 1 R3 0 1 1 R2 1 0 1 R1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N11 0 0 1 N10 0 0 1 N9 0 0 1 N8 0 0 1 N7 0 0 1 N6 0 0 1 N5 0 0 1 N4 0 0 1 N3 0 1 1 N2 1 0 1 N1 1 0 1
Note: Divide ratio less than 3 is prohibited.
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MB15E07SR
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A7 0 0 1 A6 0 0 1 A5 0 0 1 A4 0 0 1 A3 0 0 1 A2 0 0 1 A1 0 1 1
Table 5. Prescaler Data Setting
SW 1 0 Prescaler divide ratio 32/33 64/65
Table 6. Charge Pump Current Setting
CS 1 0 Current value 4.0 mA 1.0 mA
Table 7. LD/fout Output Select Data Setting
LDS 1 0 fout signal LD signal LD/fOUT output signal
(2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level (DO) is reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and DO is shown below.
Table 8. FC Bit Data Setting (LDS = "1")
FC = 1 DO fr > fP fr < fP fr = fP H L Z* fout = fr LD/fout DO L H Z* fout = fp FC = 0 LD/fout
*: High impedance
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MB15E07SR
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. When the LPF and VCO characteristics are similar to (1), set FC bit high. When the VCO characteristics are similar to (2), set FC bit low.
(1)
VCO Output Frequency
PLL
LPF
VCO
(2)
Note : Give attention to the polarity for using active type LPF.
LPF Output Voltage
3. Power Saving Mode (Intermittent Mode Control Circuit) Table 9. PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation.
11
MB15E07SR
Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s. The serial data input after the power supply becames stable, and then the power saving mode is released after completed the data input.
OFF OFF VCC VCC Clock Clock Data Data LE LE PS PS (1) (1) (2) (2) (3) (3) tV 1 s tV 1 s ON ON
tPS 100 ns tPS 100 ns
(1) PS = L (power saving mode) at Power ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: L H) 100 ns later after setting serial data.
12
MB15E07SR
SERIAL DATA INPUT TIMING
1st data Control bit Data MSB Clock LSB Invalid data
2nd data
t1 t7 LE
t2
t3 t6 t4 t5
On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter t1 t2 t3 t4 Min 20 20 30 30 Typ - - - - Max - - - - Unit ns ns ns ns Parameter t5 t6 t7 Min 100 20 100 Typ - - - Max - - - Unit ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
13
MB15E07SR
PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = "H"]
DO
[FC = "L"]
DO
Notes : * Phase error detection range: -2 to +2 * Pulses on Do signal during locked state are output to prevent dead zone. * LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 153.8 ns, fosc = 13 MHz) tWU < 4/fosc (s) (e. g. tWL < 307.7 ns, fosc = 13 MHz) * LD becomes high during the power saving mode (PS = "L").
14
MB15E07SR
MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF 1000 pF S.G. 50 fin 8 Xfin GND 7 6 DO 5 VCC 4 VP 3 N.C. OSCIN 2 1 50 0.1 F 0.1 F 1000 pF S.G.
9
10
11
12 PS
13
14
15
16
Clock Data LE Controller (setting divide ratio)
N.C. LD/fout N.C. N.C. Oscilloscope
VCC
Note: TSSOP-16
15
MB15E07SR
s TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Input sensitivity - Input frequency
10 Ta = +25 C
Input sensitivity Pfin (dBm)
0
Catalog guaranteed range
-10 -20 -30 -40 -50 0 500 1000 1500 2000 2500 3000 3500 4000 VCC = 2.7 V VCC = 3.75 V VCC = 5.0 V VCC = 5.25 V SPEC
Input frequency fIN (MHz)
2. OSCIN Input Sensitivity
Input sensitivity - Input frequency
10 Ta = +25 C
Input sensitivity VOSC (dBm)
0
Catalog guaranteed range
-10
-20
-30 VCC = 2.7 V VCC = 3.0 V VCC = 3.75 V VCC = 5.0 V SPEC 0 20 40 60 80 100 120 140 160 180
-40
-50
Input frequency fOSC (MHz)
16
MB15E07SR
3. Do output current * 1.0 mA mode
10.00
IDO - VDO
Ta = + 25 C VCC = 3.75 V Vp = 3.75 V
Charge pump output current IDO (mA)
2.000 /div
-10.00 0.00 1.00/div 7.00
Charge pump output voltage VDO (V)
* 4.0 mA mode
10.00
IDO - VDO
Charge pump output current IDO (mA)
Ta = + 25 C VCC = 3.75 V Vp = 3.75 V
2.000 /div
-10.00 0.00
1.00/div
7.00
Charge pump output voltage VDO (V)
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MB15E07SR
4. fin input impedance
4 22.184 61.264 3.9002 nH 2 500.000 000 MHz 1 : 78.328 -319.34 300 MHz 2 : 22.145 -77.82 1 GHz 3 3 : 14.324 13.364 2 GHz
4
1
2
START
300.000 000 MHz
STOP 2 500.000 000 MHz
5. OSCIN input impedance
4 32.719 -801.28 4.9656 pF 2 500.000 000 MHz 1: 633.5 -9.258 k 3 MHz
2 : 038.63 -3.0145 k 10 MHz 3 : 083.94 -1.5534 k 20 MHz 4 3 2 1
START
3.000 000 000 MHz
STOP 40.000 000 MHz
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MB15E07SR
REFERENCE INFORMATION
Test Circuit S.G. OSCIN fin Do LPF fVCO = 1730 MHz KV = 42 MHz/V fr = 200 kHz fOSC = 13 MHz LPF VCC =VP = 3.75 V VVCO = 3.3 V Ta = +25 C CP : 4.0 mA mode 27 k
Spectrum Analyzer
1000 pF VCO
2.7 k 15000 pF
120 pF
* PLL Reference Leakage
REF -10.0 dB DELTA MKR 200 kHz MKR 200 kHz -80.39 dBc NOISE/1 Hz -116.53 dBc/Hz
CENTER 1.732004 GHz RBW 3 kHz VBW 30 Hz
SWP 23 s
SPAN 1.00 MHz ATT 10 dB
* PLL Phase Noise
REF -10.0 dB DELTA MKR 10 1.00 kHz 10 VAVG 10 MKR 1.00 kHz -81.66 dBc/Hz NOISE/1 Hz -81.66 dBc/Hz
CENTER 1.73200392 GHz RBW 30 Hz VBW 100 Hz
SWP 2.0 s
SPAN 10.00 kHz ATT 10 dB
(Continued) 19
MB15E07SR
(Continued)
1730 MHz 1805 MHz within 1 kHz LchHch 390 s Mkr x : 389.98165 s y : 74.8653 MHz 100.0050 MHz 1805 MHz 1730 MHz within 1 kHz HchLch 375 s Mkr x : 375.00233 s y : -75.0818 MHz 100.0050 MHz
2.88 kHz/01v
2.88 kHz/01v
99.99500 MHz 0s 2.0000000 s
99.99500 MHz 0s 2.0000000 s
Mkr x : 389.98165 s y : 74.8653 MHz 100.0050 MHz
Mkr x : 375.08233 s y : -75.0018 MHz 250.0000 MHz
2.88 kHz/01v
50.0000 MHz/01v
99.99500 MHz 0s 2.0000000 s
0 Hz 0s 2.0000000 s
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MB15E07SR
APPLICATION EXAMPLE
LPF
VCO
OUTPUT
Lock Det.
From a controller
N.C. 16
N.C. 15
LD/fout 14
N.C. 13
PS 12
LE 11
Data 10
Clock 9
MB15E07SR
1 OSCIN
2 N.C.
3 VP
4 VCC
5 DO
6 GND
7 Xfin
8 fin 1000 pF
1000 pF 1000 pF TCXO 0.1 F 0.1 F
VP: 5.5 V Max
Note : TSSOP-16
21
MB15E07SR
USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device.
ORDERING INFORMATION
Part number MB15E07SRPFT MB15E07SRPV1 Package 16-pin, Plastic TSSOP (FPT-16P-M07) 16-pad, Plastic BCC (LCC-16P-M06) Remarks
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MB15E07SR
PACKAGE DIMENSIONS
16-pin plastic TSSOP (FPT-16P-M07) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder.
0.170.05 (.007.002)
9
*1 5.000.10(.197.004)
16
INDEX
*2 4.400.10 6.400.20 (.173.004) (.252.008)
Details of "A" part 1.050.05 (Mounting height) (.041.002) LEAD No.
1 8
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8
+0.03 +.001
(0.50(.020)) 0.600.15 (.024.006)
0.07 -0.07 .003 -.003 (Stand off) 0.25(.010)
0.10(.004)
C
2003 FUJITSU LIMITED F16020S-c-3-3
Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued)
23
MB15E07SR
(Continued) 16-pad plastic BCC (LCC-16P-M06)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.400.10 (.016.004) 0.80(.031) REF 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
INDEX AREA 3.400.10 (.134.004) 2.45(.096) TYP "A" "B" 1.15(.045) REF
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
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MB15E07SR
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0505 (c) 2005 FUJITSU LIMITED Printed in Japan

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